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general description the MAX3748/MAX3748a multirate limiting amplifier func- tions as a data quantizer for sonet, fibre channel, and gigabit ethernet optical receivers. the amplifier accepts a wide range of input voltages and provides constant- level current-mode logic (cml) output voltages with con- trolled edge speeds. a received-signal-strength indicator (rssi) is available when the MAX3748/MAX3748a is combined with the max3744 sfp transimpedance amplifier (tia). a receiver consisting of the max3744* and the MAX3748/ MAX3748a can provide up to 19db rssi dynamic range. additional features include a programmable loss-of-signal (los) detect, an optional disable function (disable), and an output signal polarity reversal (outpol). output disable can be used to implement squelch. the combination of the MAX3748/MAX3748a and the max3744 allows for the implementation of all the small- form-factor sff-8472 digital diagnostic specifications using a standard 4-pin to-46 header. the MAX3748/ MAX3748a is packaged in a 3mm ? 3mm 16-pin qfn package with an exposed pad. * future product?ontact factory for availability. applications gigabit ethernet sff/sfp transceiver modules fibre channel sff/sfp transceiver modules multirate oc-3 to oc-48-fec sff/sfp transceiver modules features ? sfp reference design available ? 16-pin qfn package with 3mm ? 3mm footprint ? single +3.3v supply voltage ? 86ps rise and fall time ? loss of signal with programmable threshold ? rssi interface (with max3744 tia) ? output disable ? polarity select ? 8.5ps p-p deterministic jitter (3.2gbps) MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier ________________________________________________________________ maxim integrated products 1 ordering information MAX3748/ MAX3748a max3744 tia* ds1858 3-input diagnostic monitor r1 3k ? c1 0.1 f in+ in- rssi th disable los 0.1 f outpol caz1 caz2 v cc gnd 4.7k ? to 10k ? los v cc _host out+ 50 ? 0.1 f out- 50 ? 0.1 f serdes r th supply filter host filter v cc _rx 4-pin to header host board sfp optical receiver *future product. t ypical operating circuits 19-2717; rev 2; 2/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package package code MAX3748ete -40? to +85? 16 qfn-ep* t1633-3 MAX3748aete -40? to +85? 16 qfn-ep* t1633-3 * ep = exposed pad. functional diagram and pin configuration appear at end of data sheet. typical operating circuits continued at end of data sheet.
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 2.97v to 3.63v, ambient temperature = -40c to +85?, cml output load is 50 ? to v cc , c az = 0.1?, typical values are at +25?, v cc = 3.3v, unless otherwise specified. the data input transition time is controlled by a 4th-order bessel filter with f -3db = 0.75 ? 2.667ghz for all data rates of 2.667gbps and below, and with f -3db = 0.75 ? 3.2ghz for a data rate of 3.2gbps.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) .................................-0.5v to +6.0v voltage at in+, in- ..........................(v cc - 2.4v) to (v cc + 0.5v) voltage at disable, outpol, rssi, caz1, caz2, los, th............................-0.5v to (v cc + 0.5v) current into los ...................................................-1ma to +9ma differential input voltage (in+ - in-) .....................................2.5v continuous current at cml outputs (out+, out-) ...............................................-25ma to +25ma continuous power dissipation (t a = +70?) 16-pin qfn (derate 17.7mw above +70?) ....................1.4w operating junction temperature range (t j ) ....-55? to +150? storage ambient temperature range (t s ) ........-55? to +150? parameter symbol conditions min typ max units single-ended input resistance single ended to v cc 42 50 58 ? input return loss differential, f < 3ghz, dut is powered on 13 db input sensitivity v in-min (note 1) 5 mv p-p input overload v in-max (note 1) 1200 mv p-p single-ended output resistance single ended to v cc 42 50 58 ? output return loss differential, f < 3ghz, dut is powered on 10 db differential output voltage 600 780 1200 mv p-p differential output signal when disabled outputs ac-coupled, v in-max applied to input (note 2) 10 mv p-p k28.5 pattern at 3.2gbps 8.5 25 2 23 - 1 prbs equivalent pattern at 2.7gbps (note 4) 9.3 30 k28.5 pattern at 2.1gbps 7.8 25 deterministic jitter (notes 2, 3) dj 2 23 - 1 prbs equivalent pattern at 155mbps 25 50 ps p-p input = 5mv p-p 6.5 random jitter (note 5) input = 10mv p-p 3 ps rms data output transition time 20% to 80% (note 2) 86 115 ps input-referred noise 185 ? rms c az = open 70 low-frequency cutoff c az = 0.1? 0.8 khz (note 6) 32 49 power-supply current i cc los disabled 37 ma power-supply noise rejection psnr f < 2mhz 26 db loss of signal at 2.5gbps (notes 2, 7) los hysteresis 10l og ( v d e a s s e r t /v a s s e r t ) 1.25 2.2 db los assert/deassert time (note 8) 2 100 ? low los assert level r th = 20k ? 2.8 4.1 mv p-p low los deassert level r th = 20k ? 6.7 11.6 mv p-p medium los assert level r th = 280 ?
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 3 note 1: between sensitivity and overload, all ac specifications are met. note 2: guaranteed by design and characterization. note 3: the deterministic jitter caused by this filter is not included in the dj generation specifications (input). note 4: 2 23 - 1 prbs pattern was substituted by k28.5 pattern to determine the high-speed portion of the deterministic jitter. the low-speed portion of the dj (baseline wander) was obtained by measuring the eye width difference between outputs gen- erated using k28.5 and 2 23 - 1 prbs patterns. note 5: random jitter was measured without using a filter at the input. note 6: the supply current measurement excludes the cml output currents by connecting the cml outputs to a separate v cc (see figure 1). note 7: unless otherwise specified, the pattern for all los detect specifications is 2 23 - 1 prbs. note 8: the signal at the input is switched between two amplitudes, signal_on and signal_off, as shown in figure 2. note 9: i cm_input is the input common mode. i rssi is the current at the rssi output. note 10: stability is defined as variation over temperature and power supply with respect to the typical gain of the part. electrical characteristics (continued) (v cc = 2.97v to 3.63v, ambient temperature = -40c to +85?, cml output load is 50 ? to v cc , c az = 0.1?, typical values are at +25?, v cc = 3.3v, unless otherwise specified. the data input transition time is controlled by a 4th-order bessel filter with f -3db = 0.75 ? 2.667ghz for all data rates of 2.667gbps and below, and with f -3db = 0.75 ? 3.2ghz for data rate of 3.2gbps.) parameter symbol conditions min typ max units medium los deassert level r th = 280 ? 25 38.6 mv p-p high los assert level r th = 80 ? ? loss of signal at 155mbps (note 7) los hysteresis 10log ( v d e a s s e r t /v a s s e r t ) 2.1 db los assert/deassert time (note 8) 20 ? low los assert level r th = 20k ? 3.5 mv p-p low los deassert level r th = 20k ? 5.6 mv p-p medium los assert level r th = 280 ? ? ? ? rssi rssi current gain (note 9) a rssi a rssi = i rssi /i cm_rssi 0.03 i cm_input < 6.6ma -31 +33 input-referred rssi current stability i rssi /a rssi (note 10) i cm_input > 6.6ma -73 +90 ? ttl/cmos i/o los output high voltage v oh r los = 4.7k ? to10k ? to v cc_host (3v) 2.4 v los output low voltage v ol r los = 4.7k ? to10k ? to v cc_host (3.6v) 0.4 v los output current r los = 4.7k ? to10k ? to v cc_host (3.3v); ic is powered down 40 ? disable input high v ih 2.0 v disable input low v il 0.8 v disable input current r los = 4.7k ? to 10k ? to v cc_host 10 ?
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier 4 _______________________________________________________________________________________ t ypical operating characteristics (t a = +25? and v cc = +3.3v, unless otherwise specified.) supply current vs. temperature MAX3748 toc01 temperature ( c) current (ma) 90 80 60 70 -10 0 10 20 30 40 50 -30 -20 10 20 30 40 50 60 70 80 90 100 0 -40 100 transfer function MAX3748 toc02 differential input (mv p-p ) differential output (mv p-p ) 5 4 3 2 100 200 300 400 500 600 700 800 900 0 16 output voltage vs. input voltage random jitter vs. temperature (input level 10mv p-p ) MAX3748 toc03 temperature ( c) random jitter (ps rms ) 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 2 4 3 1 6 8 9 7 5 10 0 -40 100 random jitter vs. input amplitude MAX3748 toc04 differential input amplitude (mv p-p ) random jitter (ps rms ) 30 20 10 1 2 3 4 5 6 7 8 9 10 0 040 bit-error ratio vs. input voltage MAX3748 toc05 input voltage (mv p-p ) bit-error ratio (10 -12 ) 4.5 4.0 3.5 3.0 2.5 200 400 600 800 1000 1200 0 2.0 5.0 deterministic jitter vs. input common-mode voltage (v cc to v cc - 0.8v) MAX3748 toc06 common-mode voltage (v cc + x) deterministic jitter (ps p-p ) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 12 14 16 18 20 22 24 10 -1.0 0 output eye diagram (minimum input) MAX3748 toc07 50ps/div 100mv/div 3.2gbps, 2 23 - 1 prbs, 5mv p-p output eye diagram (maximum input) MAX3748 toc08 50ps/div 100mv/div 3.2gbps, 2 23 - 1 prbs, 1200mv p-p output eye diagram (minimum input) MAX3748 toc09 100ps/div 100mv/div 2.7gbps, 2 23 - 1 prbs, 5mv p-p
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 5 output eye diagram with maximum input (data rate of 2.6667gbps) MAX3748 toc10 50ps/div 100mv/div 2.7gbps, 2 23 - 1 prbs, 1200mv p-p output eye diagram at +100 c (minimum input) MAX3748 toc11 50ps/div 100mv/div 3.2gbps, 2 23 - 1 prbs, 5mv p-p assert/deassert levels vs. r th MAX3748 toc12 r th (k ? ) assert/deassert (mv p-p ) 0.1 1 10 10 100 1 0.01 100 assert deassert input return gain vs. frequency (sdd11) (input signal level = -40dbm) MAX3748 toc13 frequency (hz) gain (db) 1g -30 -20 -10 0 10 20 30 -40 100m 10g output disabled output return gain vs. frequency (sdd22) (input signal level = -40dbm) MAX3748 toc14 frequency (hz) gain (db) 1g -30 -20 -10 0 10 20 30 -40 100m 10g deterministic jitter vs. input offset voltage (2.667gbps, k28.5) MAX3748 toc15 input offset voltage (mv p-p ) deterministic jitter (ps p-p ) 4 2 0 -2 -4 2 4 6 8 10 12 14 16 18 20 0 -6 6 los hysteresis vs. temperature (2.667bps, 2 10 - 1 prbs) MAX3748 toc16 temperature ( c) 10log (deassert/assert) (db) 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 1 2 3 4 5 6 0 -40 100 r th = 20k ? r th = 80 ? r th = 280 ? 0 200 100 400 300 600 500 700 0400 200 600 800 100 500 300 700 900 1000 rssi current gain vs. input tia current (max3744 and MAX3748) MAX3748 toc17 input tia current ( a) output rssi current ( a) t ypical operating characteristics (continued) (t a = +25? and v cc = +3.3v, unless otherwise specified.)
MAX3748/MAX3748a detailed description the limiting amplifier consists of an input buffer, a multi- stage amplifier, offset correction circuitry, an output buffer, power-detection circuitry, and signal-detect cir- cuitry (see functional diagram ). input buffer the input buffer is shown in figure 3. it provides 50 ? termination for each input signal in+ and in-. the MAX3748/MAX3748a can be dc- or ac-coupled to a tia (tia output offset degrades receiver performance if dc-coupled). the cml input buffer is optimized for the max3744 tia. gain stage the high-bandwidth gain stage provides approximately 53db of gain. compact 155mbps to 3.2gbps limiting amplifier 6 _______________________________________________________________________________________ pin description pin name function 1, 4, 12 v cc supply voltage 2 in+ noninverted input signal, cml 3 in- inverted input signal, cml 5th loss-of-signal threshold pin. resistor to ground (r th ) sets the los threshold. connecting this pin to v cc disables the los circuitry and reduces power consumption. 6 disable disable input, cmos/ttl. the data outputs are held static when this pin is asserted high. the los function remains active when the outputs are disabled, cmos. on the MAX3748, this pin does not include esd protection. if routed through the ds1858/ds1859 controller ic, no additional esd protection is required. on the MAX3748a, this pin has esd protection. 7 los noninverted loss-of-signal output. los is asserted high when the signal drops below the assert threshold set by the th input. the output is open collector (figure 5). on the MAX3748, this pin does not include esd protection. if routed through the ds1858/ds1859 controller ic, no additional esd protection is required. on the MAX3748a, this pin has esd protection. 8, 16 gnd supply ground 9 outpol output polarity control input. connect to gnd for an inversion of polarity through the limiting amplifier and connect to v cc for normal operation. 10 out- inverted data output, cml 11 out+ noninverted data output, cml 13 rssi received-signal-strength indicator. this current output can be used to obtain a ground-referenced voltage proportional to photodiode current with the max3744 by connecting an external resistor between this pin and gnd. 14 caz2 offset correction loop capacitor connection. a capacitor connected between this pin and caz1 extends the time constant of the offset correction loop. typical value of c az is 0.1?. the offset correction is disabled when the caz1 and caz2 pins are shorted together. 15 caz1 o ffset c or r ecti on loop c ap aci tor c o nnecti on. a cap aci tor connected b etw een thi s p i n and c az 2 extend s the ti m e constant of the offset cor r ecti on l oop . typ i cal val ue of c a z i s 0. 1?. the offset cor r ecti on i s d i sab l ed w hen the c az 1 and c az 2 p i ns ar e shor ted tog ether . ep exposed paddle connect the exposed paddle to board ground for optimal electrical and thermal performance. v cc i cc (supply current) i out (cml output current) 50 ? r th 50 ? MAX3748/ MAX3748a figure 1. power-supply current measurement
offset correction loop the MAX3748/MAX3748a is susceptible to dc offsets in the signal path because it has high gain. in commu- nication systems using nrz data with a 50% duty cycle, pulse-width distortion present in the signal or generated in the transimpedance amplifier appears as an input offset and is reduced by the offset correction loop. for gigabit ethernet and fibre channel applica- tions, no capacitor is required. for sonet applications, c az = 0.1? is recommended. this capacitor deter- mines the lower 3db frequency of the data path. cml output buffer the MAX3748/MAX3748a limiting amplifier? cml out- put provides high tolerance to impedance mismatches and inductive connectors. the output current is approx- imately 18ma. the output is disabled by connecting the disable pin to v cc . if the los pin is connected to the disable pin, the outputs out+ and out- are at a stat- ic voltage (squelch) whenever the input signal level drops below the los threshold. the output buffer can be ac- or dc-coupled to the load (figure 4). power-detect and loss-of-signal indicator the MAX3748/MAX3748a is equipped with an los cir- cuitry, which indicates when the input signal is below a programmable threshold, set by resistor r th at the th pin (see typical operating characteristics for appropri- ate resistor sizing). an averaging peak-power detector compares the input signal amplitude with this threshold and feeds the signal detect information to the los out- put, which is open collector. two control voltages, v assert and v deassert , define the los assert and deassert levels. to prevent los chatter in the region of the programmed threshold, approximately 2db of hys- teresis is built into the los assert/deassert function. once asserted, los is not deasserted until the input amplitude rises to the required level (v deassert ) (figure 5). design procedure program the los assert threshold external resistor r th programs the los threshold. see the assert/deassert levels vs. r th graph in the typical operating characteristics to select the appropriate resistor. MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________________________ 7 1db 6db 0v signal on max deassert level min deassert level power-detect window v in time signal off figure 2. los deassert threshold set 1db below the minimum by receiver sensitivity (for selected r th ) 50 ? 50 ? 75k ? in+ in- 0.25pf 0.25pf v cc esd structures figure 3. cml input buffer q3 q4 q1 v cc 50 ? 50 ? q2 18ma 18ma disable disable disable data out+ out- esd structures figure 4. cml output buffer
MAX3748/MAX3748a select the coupling capacitor when ac-coupling is desired, coupling capacitors c in and c out should be selected to minimize the receiver? deterministic jitter. jitter is decreased as the input low- frequency cutoff (f in ) is decreased: f in = 1 / [2 (50)(c in )] for atm/sonet or other applications using scrambled nrz data, select (c in , c out ) 0.1?, which provides f in < 32khz. for fibre channel, gigabit ethernet, or other applications using 8b/10b data coding, select (c in , c out ) 0.01?, which provides f in < 320khz. refer to application note hfan-1.1: choosing ac- coupling capacitors . select the offset-correction capacitor the capacitor between caz1 and caz2 determines the time constant of the signal path dc offset cancellation loop. to maintain stability, it is important to keep a one- decade separation between f in and the low-frequency cutoff (f oc ) associated with the dc offset cancellation circuit. for atm/sonet or other applications using scrambled nrz data, f in < 32khz, so f ocmax < 3.2khz. therefore, c az = 0.1? (f oc = 2khz). for fibre channel or gigabit ethernet applications, leave pins caz1 and caz2 open. rssi implementation the sff-8472 digital diagnostic specification requires monitoring of input receive power. the MAX3748/ MAX3748a and max3744 receiver chipset allows for the monitoring of the average receive power by mea- suring the average dc current of the photodiode. the max3744 preamp measures the average photodi- ode current and provides the information to the output common mode. the MAX3748/MAX3748a rssi detect block senses the common-mode dc level of input sig- nals in+ and in- and provides a ground-referenced out- put signal (rssi) proportional to the photodiode current. the advantage of this implementation is that it allows the tia to be packaged in a low-cost conventional 4-pin to- 46 header. the MAX3748/MAX3748a rssi output is connected to an analog input channel of the ds1858/ds1859 sfp controller to convert the analog information into a 16-bit word. the ds1858/ds1859 provide the receive-power information to the host board of the optical receiver through a 2-wire interface. the ds1859 allows for internal calibration of the receive-power monitor. the max3744 and the MAX3748/MAX3748a have been optimized to achieve rssi stability of 2.5db within the range of 6? to 500? of average input photodiode current. to achieve the best accuracy, maxim recom- mends receive power calibration at the low end (6?) and the high end (500?) of the required range; see the rssi current gain graph in the typical operating characteristics . connecting to the ds1858/ds1859 for best use of the rssi monitor, capacitor c1 and resistor r1 shown in the first typical application circuit need to be placed as close as possible to the dallas diagnostic monitor with the ground of c1 and r1 the same as the ds1858/ds1859 ground. capacitor c1 suppresses system noise on the rssi signal. r1 = 3k ? and c1 = 0.1? is recommended. compact 155mbps to 3.2gbps limiting amplifier 8 _______________________________________________________________________________________ gnd esd structure v cc los figure 5. MAX3748 los output circuit gnd esd structure v cc los figure 6. MAX3748a los output circuit
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier _______________________________________________________________________________________ 9 max3744 tia ds1858 3-input diagnostic monitor r1 3k ? c1 0.1 f in+ in- rssi th disable los 0.1 f outpol caz1 caz2 v cc gnd 4.7k ? to 10k ? v cc_host los out+ 50 ? 0.1 f out- 50 ? 0.1 f serdes r th supply filter host filter v cc_rx 5-pin to header host board sfp optical receiver pin or apd v cc (+3.3v or apd reference voltage) v cc (+3.3v) MAX3748/ MAX3748a t ypical operating circuits (continued) max3744 tia ds1858 3-input diagnostic monitor in+ in- rssi th disable los 0.1 f outpol caz1 caz2 v cc gnd 4.7k ? to 10k ? v cc_host los out+ 50 ? out- 50 ? c in 0.1 f c out 0.1 f c out 0.1 f c in 0.1 f serdes r th supply filter host filter v cc_rx 5-pin to header host board sfp optical receiver pin or apd v cc (+3.3v or apd reference voltage) v cc (+3.3v) high-side current sense MAX3748/ MAX3748a
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier 10 ______________________________________________________________________________________ chip information transistor count: 1468 process: sige bipolar 16 1 2 3 4 gnd v cc in+ in- v cc v cc out+ out- outpol 15 caz1 14 caz2 13 5 6 7 8 12 11 10 9 rssi th disable los gnd 3mm x 3mm qfn MAX3748/ MAX3748a pin configuration 50 ? 50 ? out- out+ v cc 50 ? 50 ? v cc 18ma disable offset correction caz1 caz2 c az rssi detect power detect rssi in- in+ th los outpol MAX3748/ MAX3748a functional diagram
MAX3748/MAX3748a compact 155mbps to 3.2gbps limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 1. dimensioning & tolerancing conform to asme y14.5m-1994. exposed 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220 revision c. notes:

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